In high speed VLSI systems, wiring is an important parameter as it may generate unuseful internal delays which directly impact the global performance of the system. Due to chip design constraints, the signals propagate on different paths and race conditions are often occurring, leading to overlapped operations. The worst case delays are often taken as reference delays for synchronization of signals, and generally a clock or a control signal based on this reference delay is gating the circuits to be selected. Moreover, a time margin is most often added to the worst case reference delay to be sure that all switching of signals are ended before the gating signal becomes active.
The general state of the prior art with respect to solving the race conditions problem may be best illustrated and understood with reference to several patents described now.
U.S. Pat. No. 5,121,005 discloses a programmable logic array (PLA) wherein the propagation paths for the control signals are made slower than the worst case data path to eliminate race conditions. The PLA operates with a single clock signal frequency which delays the control signals allowing time for the signals to reach steady state.
U.S. Pat. No. 5,124,572 discloses a clocking methodology using global overlapping clocks for providing timing advantages and locally non-overlapping clocks derivative from the overlapping clocks for eliminating race conditions.
In U.S. Pat. No. 4,544,850, a mediator circuit is used to prevent gate delay variations from causing processing to commence after a period of time during which data is made available. The mediator circuit outputs a gated data signal provided by a data enable signal and a data signal.
In the decoders, and particularly in high speed decoders the aforementioned problem is crucial as only one line (a wordline or a pair of bitlines) has to be selected among all, otherwise a wrong data is read from or written into the memory array.
Usually, with a large number of address inputs, the decoder is split in several stages referred to as predecoder, decoder, driver, wherein the address paths are different for each stage. As a result, mistracking along these different address paths could occur, so time margins are absolutely required in order to avoid race conditions. Unfortunately these time margins are directly added to the access time, and thus decrease the overall system speed performance.
In the known multi-stage decoders, the time margin is usually added to the delay of the decoder/driver stage. A clock signal applied to the input of this stage becomes active when all predecoding signals have reached a steady state, allowing only one line to be selected.
Referring to FIG. 1A, a two-stage word decoder of the prior art particularly adapted for use in high speed memories, is illustrated. The specific details of operation of this system, which are well understood by those skilled in the art, will be omitted from this discussion. The devices of the predecoder stage are connected according to the so-called NOR-type logic, which is a fast decoding architecture. The devices of the decoder/driver stage are connected according to the so-called NAND-type logic. For simplification of the description, a 4-bit row decoding circuit is shown but the principle now described may be applied to any other x-bit row or column decoding circuit, as well as to devices processed by different technologies.
Briefly described, the predecoder stage is composed of 16 blocks, each block having four NFET devices receiving true or complement address bits (A1T/C-A4T/C) being distributed according to a binary code table as the one of FIG. 1B.
A PFET device connected to the output of each predecoder block receives a RESET signal to tie to a high level V+ all the NOR output nodes (OUT1-OUT16) when the circuit is not active i.e., when no decoding operation is required.
Each of the sixteen decoder/driver blocks consists of a 2.times.ways NAND gate which receives on a first input the corresponding output from the predecoder block and on a second input an asynchronous clock signal CLK. The clock signal gates the final selection of a wordline (one among the sixteen WL1-WL16).
When a cycle for selecting a wordline is initiated, the RESET signal is tied to a high level V+. According to the binary state applied on the gate of the NFET devices of each predecoder block, fifteen outputs predecoder go down to a low voltage while only one output remains high. Then the CLK signal becomes active when the slowest NOR circuit output has been discharged (i.e., the one with only one active NFET device).
Even such a decoding architecture is very fast, it suffers from a risk of a multiselection wordline in case the CL signal becomes valid before the fifteen deselections. And a time margin is added along the path of the CLK signal, such as the circuit of FIG. 2, to delay the gating of the decoder/driver stage. This solution limits the risk of a multi selection, but it does not eliminate it. Unfortunately the gating delay decreases the speed performance of the system.
The drawback of such solution is that the performance of the decoder is both impacted by the longest delay in the predecoder stage moreover the delay of the time margin. Furthermore, it does not give the assurance of preventing a hazard timing from occurring, except if an excessive delay is chosen for the time margin applied to the clock signal, but it does not comply with the nowadays high speed systems.
None of the Cited references, which exemplify the state of the art, teach, claim or even suggest a circuit for avoiding race conditions to be used in connection with decoder systems.
Accordingly, it would be desirable to be able to provide a new and improved decoder which eliminates the aforementioned delay resulting from race condition.